1. Field of the Invention
The present invention relates to a method and apparatus for designing a semiconductor integrated device, and more particularly, to a method and apparatus for arranging power supply cells in an input/output circuit area of the semiconductor integrated device.
2. Description of the Related Art
Generally, a semiconductor integrated device is partitioned by an internal circuit area and an input/output circuit area surrounding the internal circuit area. The input/output circuit area includes power supply cells and input/output buffers.
The power supply cells receive power supply voltages via pads from the exterior and supply the power supply voltages via power supply lines to the input/output buffers as well as the internal circuit area.
The input/output buffers are connected via pads to external devices, so that the input/output buffers carry out signal transmission between the semiconductor integrated device and the external devices.
In the above-mentioned semiconductor integrated device, noise currents may be generated. That is, when a plurality of input/output buffers are simultaneously switched by the same operating frequency, a simultaneous switching noise (SSN) current may be generated in the input/output buffers between the power supply lines. Also, when circuits in the internal circuit area are operated, a radiant noise current may be generated.
In order to decrease the above-mentioned simultaneous switching noise current, in a prior art semiconductor integrated device designing method (see: JP-2005-196406 A), first, a frequency-to-impedance characteristic curve between two power supply lines is calculated in accordance with circuit design data for a semiconductor integrated device (chip). In this case, assume that a resonant frequency at which the impedance is maximum is very close to the operating frequency of the semiconductor integrated device, so that the noise current would be remarkably increased. Next, the resonant frequency is decreased or increased by increasing or decreasing the inductance and/or capacitance between the power supply lines, to decrease the noise current. Thus, the circuit design data is changed in accordance with the frequency-to-impedance characteristics between the power supply lines and the operating frequency of the semiconductor integrated device, to decrease the noise current. This will be explained later in detail.